1. Field of the Invention
The present invention relates to a multiport cache memory in which two types of ports are provided for reducing the structure thereof.
2. Description of the Background Art
In general, as shown in FIG. 1, a conventional CPU 1 for accessing to a main memory 2 comprises:
an internal arithmetic circuitry 3; and PA1 a cache memory 4 for exchanging data or instructions with the main memory 2 at the low access speed of the main memory 2 and exchanging the data or the instructions with the arithmetic circuitry 3 at the high speed of the arithmetic circuitry 3. The main memory 2 is provided with large scale dynamic random access memory (DRAM). PA1 a plurality of internal arithmetic circuitries 3; and PA1 a cache memory 6 for exchanging data or instructions with the main memory 2 at the low access speed of the main memory 2 and exchanging data or the instructions with the arithmetic circuitries 3 at the high speed of the arithmetic circuitries 3. PA1 a plurality of read only ports for respectively transmitting data or instructions to each arithmetic circuitry according to the load instruction; and PA1 a plurality of read/write ports for respectively transmitting data or instructions from/to each arithmetic circuitry according to the load or store instruction.
In the above configuration, the arithmetic processing speed in the arithmetic circuitry 3 is not regulated by the low access speed in the main memory 2 because the arithmetic circuitry 3 exchanges the data or instructions with the cache memory 4.
However, even if the clock cycle is shortened, it is difficult to improve processing capacity other than by shortening the clock cycle because only one piece of data or one instruction can be executed in a clock cycle in the above conventional CPU.
Therefore, as shown in FIG. 2, another conventional CPU 5 for accessing to a main memory 2 comprises:
In the above configuration, a plurality of data or instructions are processed in parallel.
Accordingly, processing capacity can be improved by means other than shortening the clock cycle because the plurality of data or instructions can be processed in parallel.
However, in the above configuration, it sometimes occurs that the plurality of internal arithmetic circuitries 3 simultaneously access the cache memory 6. In this case, if the cache memory 6 is provided with only one input/output port for the plurality of internal arithmetic circuitries 3, only one internal arithmetic circuitry 3 can access the cache memory 6, at a given time.
Therefore, arithmetic processing in most of the arithmetic circuitries 3, which can not access the cache memory 6, is stopped and processing capacity declines. Also, a complicated configuration is needed for determining the order of memory access from each arithmetic circuitry 3.
Therefore, if the cache memory 6 is changed to a multiport cache memory and each arithmetic circuitry 3 can independently access cache memory 6, the drawback in the conventional CPU 5 is solved and the advantage of the plurality of arithmetic circuitries 3 is demonstrated.
However, when the multiport cache memory is utilized with to the plurality of arithmetic circuitries 3, either a load instruction or a store instruction according to the arithmetic processing in the arithmetic circuitry 3 is provided to each port of the multiport cache memory. Therefore, in the ports of the multiport cache memory, both the load and store instructions must be processed respectively. That is, each port of the multiport cache memory comprises a read/write port in which read operation and write operation are capable.
Accordingly, when all of the ports in the multiport cache memory are configured as read/write ports, the number of wires connected to a memory cell 7 increases so that the area occupied by each port of the multiport cache memory increases as shown in FIG. 3.
Moreover, as shown in FIG. 3, data input/output operation between the memory cell 7 and the external circuitry is executed through a pair of bit lines. Therefore, doubling the number of bit lines so the likelihood increases of mutual interference between bit lines. As a result, the circuit design is complicated to prevent unstable access operation.